The Cost of Multiple Exposures: Why China's Chip Strategy Is Getting Expensive

Three. That is the number of exposures on a 193 immersion tool that experts say costs about the same as a single pass on an extreme ultraviolet machine. According to industry wisdom, the balance shifts at four masks, where EUV becomes the cheaper option. For Chinese chipmakers locked out of ASML’s latest equipment, this mathematical threshold defines the growing financial pressure of their production methods. The shift forces manufacturers to accept higher costs and lower efficiency to keep pace with global technology standards.

Export controls have prevented ASML’s EUV lithography systems from entering China, leaving local firms dependent on older deep ultraviolet equipment. These older machines can still produce capable silicon by exposing critical chip layers multiple times. However, this approach creates more opportunities for defects and extends production times. As a result, the bills for manufacturers rise with every additional step in the process.

The reliance on DUV is not without precedent in high-performance computing. A 2023 teardown of Huawei’s Mate 60 Pro revealed that its Kirin 9000S processor was fabricated by SMIC using a second-generation 7nm-class process without EUV. More recent analysis suggests SMIC has advanced its DUV-based process closer to 5nm densities. While this progress is notable, it still trails the leading processes from TSMC and Samsung. Some analysts estimate the gap between China and the West in this specific area is five years or more.

The technique driving this progress is known as multiple patterning. Instead of printing a complex layer in one pass, manufacturers break the design into simpler patterns and build the layer step by step. Chris Mack, co-founder and CTO of Fractilia, notes that the ability to make a chip without EUV often ignores the significant trade-offs involved. Each new pattern must align precisely with previous etching. More exposures mean more accumulated overlay errors and process variation.

To compensate for these alignment issues, designers often add space around features. This enlarges the chip and reduces the number of dies per wafer. Given that wafers cost tens of thousands of dollars each, this is a costly outcome. Mack emphasizes that manufacturers do not sell wafers; they sell die. This distinction highlights the financial penalty of using DUV for advanced nodes.

Memory production provides further evidence of the efficiency gap. A June report by Morgan Stanley estimated that Chinese DRAM maker CXMT produces only about one-third as many bits per wafer as its Western rivals. The bank described lithography access as a hard ceiling for Chinese memory development. Mack also cautioned that node labels like 5nm or 3nm have limited meaning on their own. SMIC’s N+3 process, while a step forward, remains significantly less scaled than established 5nm processes from major competitors.

Despite these constraints, DUV technology still has room to run. Micron developed its 1-alpha DRAM without EUV by using multiple patterning and tight process control. Mack noted that Micron pushed 193 immersion farther than any other memory maker. Morgan Stanley considers CXMT’s planned move to 1-alpha DRAM achievable without EUV. Researchers expect advanced packaging to allow firms to use DUV for the latest DRAM generations by the end of the decade.

The path forward for China involves accepting larger dies, poorer yields, or longer manufacturing times. Morgan Stanley assumes CXMT will stay on 1-alpha without EUV but expects its share of global DRAM bit supply to rise from 14% in 2026 to 16% in 2028 through new capacity. The bank also predicts China’s AI chip self-sufficiency will jump from 42% in 2025 to 70% by 2030. While EUV, HBM, and advanced software will leave a persistent gap, the strategy allows for continued growth despite the rising costs of every extra exposure.